Clock forwarded architectures help to achieve higher data rates due to jitter tracking between transmitted data and the clock signals. Further, higher data rates can be achieved by using quadrature data rate i.e., transmitting data on rising and falling edges of a pair of quadrature clocks e.g., ICLK/QCLK.
In this context, it is important to maintain a desired duty-cycle of the two clock signals, and a desired phase, e.g., a quadrature-phase (90° lag) relationship between them. In some situations, the transmitter-receiver loop traverses two or more devices. For example, control of the duty-cycle and phase shift may be performed in a Memory Controller PHY, while detection of duty-cycle/phase error is performed in the Memory PHY. A precise 50% duty cycle and quadrature-phase relation of the clock signals helps to reduce data recovery error rates and therefore improve effective transmission rates.